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binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Xcelium support for Agilex P-tile PCIe simulations

Hi there, I am creating a PCIe controller targeting Agilex F series device. Wanted to run the example design on Cadence Xcelium simulator. When I ran the generated script for Xcelium, I got the belo...
Simulation
  • binupr's avatar
    binupr
    3 years ago

    Hi Wincent,

    Apologies for the delay in responding to your prior follow-up email.

    Yes, you can close this ticket.

    Thank you for the support.

    Regards

    Binu

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Binu,

Thanks for that,
We have some update in the newest version of Quartus, I am not sure that this able to solve the issue you seeing.
But the good start is you not seeing the earlier error anymore.
if you still seeing the same error using v23.2. Please sent me the .qar file together with any testbench file.

I will file this to related team.

Regards,

Wincent_Intel

binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hi Wincent,

I was finally able to get the simulation finishing and passing in Quartus 23.2_pro. So we will upgrade our internal version to 23.2_pro. I had to also put the IP in Gen5, 1x16, 1024 bit mode. Looks like that is one of the only 2 modes supported by example design.

Finally, I have couple of additional questions.

  1. Can you check and confirm if there are any fundamental functionality differences between a P-tile and R-tile IP?
    • Say for example, if I generate a R-tile IP in Gen3,2x8 mode with TLP header enabled in GUI and this works in simulation, can I replace it with a P-tile Gen3, 2x8 mode IP later if needed and expect same functionality?
  2. Related to the above question, is the R-tile IP interface backward compatible to a P-tile IP interface?

Thanks

Binu