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binupr's avatar
binupr
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
Solved

Xcelium support for Agilex P-tile PCIe simulations

Hi there, I am creating a PCIe controller targeting Agilex F series device. Wanted to run the example design on Cadence Xcelium simulator. When I ran the generated script for Xcelium, I got the belo...
Simulation
  • binupr's avatar
    binupr
    3 years ago

    Hi Wincent,

    Apologies for the delay in responding to your prior follow-up email.

    Yes, you can close this ticket.

    Thank you for the support.

    Regards

    Binu

Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Yes you are right.

If for R-tile it did support as per mention in the user guide in the latest version of Quartus

But for P-tile, it may be supported in future releases (Subject to change), so the error you see in P-tile is expected.


Let me know if you need any further clarification.


Regards,

Wincent_Intel


  • binupr's avatar
    binupr
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Hi,

    Looks like you missed couple of questions from my previous message. Please see the highlighted section from below screenshot. Could you clarify those?

    Thanks

    Binu