ThomasTessier
Occasional Contributor
1 year agoXcelium Simulation of Agile5 design FATAL when entering Simulation?
I have a very large DUT mixed-signal environment that I am integrating into with a new Agile5 FPGA design. I have this environment working with the Arria5 in previous generations. So this is entirely focused on the Agile5.
This appears to be focused on the new "tennm" libraries in some why but I cannot seem to figure out what Xcelium switch (or combination) I am missing.
Below is a screen shot of the FATAL that is happening in simulation. I am unsure what is meant by the "-SV_LIB" switch and the shared object?
Any assistance would be welcome.
TomT...