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ThomasTessier's avatar
ThomasTessier
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1 year ago

Xcelium Simulation of Agile5 design FATAL when entering Simulation?

I have a very large DUT mixed-signal environment that I am integrating into with a new Agile5 FPGA design. I have this environment working with the Arria5 in previous generations. So this is entirely...
Simulation
ThomasTessier's avatar
ThomasTessier
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Still not solved, but I did run the canned xcelium_setup.sh created in our Platform Designer block in the QSYS_DIR/sim/xcelium_setup.sh. When running this script I modified it to show me the commands which are being executed for xmelab and xmsim. I do not see the switch "-sv_lib" set in this conditions and the simulation runs to completion.

So this is the actual FPGA design which is not instantiated with our Testbench and DUT. The one difference that I notice is that there is a "libdpi.so" in this directory so it is just picking up this default name and location. Our environment is a little more complex because we also do incremental compile for the design as the various DUT pieces take quite some time.

So I am still a little baffled given that I am able to run the UNIT simulation created by QUARTUS for our FPGA and it runs fine with any additional switches.

Any thoughts?

TomT...