Wrong node type for node in vector source file (vhdl file). Jk flop

Design node type is of Output type but in signal in vector file is bidirectional. (QUARTUS II)

My code for a JK flip flop compiles correctly but the problem I am having is that when I try to run simulation, an error occurs. I've been troubleshooting/debugging for 2 days now with no luck. Any advice?

entity jkflop is

port (

j,k,clk,pre,clr: in bit;

q, qn: out bit);

end jkflop;

architecture behavior of jkflop is

begin

PROCESS(clk,pre,clr)

variable q1: bit;

begin

if pre = '0' then

q1:= '1';

elsif clr = '0' then

q1:= '0';

elsif (clk 'event AND clk = '0') then

if (j = '0' AND k = '0') then

q1:= q1;

elsif (j = '1' AND k = '0') then

q1:= '1';

elsif (j = ''0' AND k = '1') then

q1:= '0';

else

q1:= NOT q1;

END if;

END if;

q<= q1;

qn<= NOT q1;

END PROCESS;

END behavior;