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Altera_Forum
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11 years ago

Wrong node type for node in vector source file (vhdl file). Jk flop

Design node type is of Output type but in signal in vector file is bidirectional. (QUARTUS II) My code for a JK flip flop compiles correctly but the problem I am having is that when I try to ru...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Your vwf isnt setup correctly. I highly suggest you write your own testbench rather than try and use a VWF file for testing.