Altera_Forum
Honored Contributor
10 years agowork flow creating IP component from vhdl in Qsys
Hi i experience some confusing behavior when i work with Qsys and Quartus to create/modify vhdl files used in IP components used in qsys. Here is what i do..
1) edit vhdl file used in Component "MySomething" in Quartus (This file is included in my Quartus project, not sure if it has to be ? properly not) 2) to update my system with the change, i open Qsys and click generate HDL 3) remove old .qip file in Quartus project and add new to project 4) "Ctrl+L" to start compilation 5) download .sof file 6) Open my NIOS debug project 7) right click on project_bsp->index->rebuild all 8) right click on project_bsp->NIOSII->generate BSP 9) right click on project->index->rebuild all 10) start debugger via JTAG is this the correct work flow for update of IP components ? heres the Problem. when i make an update to my vhdl file and saves it, then start Analysis and Synthesis, it used another version the component file. Where is this file stored ? how do i update it ? thanks in advance