work flow creating IP component from vhdl in Qsys

Hello,

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when i make an update to my vhdl file and saves it, then start Analysis and Synthesis, it used another version the component file. Where is this file stored ? how do i update it

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When ever you select 'Generate HDL' for your system in Qsys, Qsys copies your files from original location to 'submodules' folder in your project. 'submodules' folder is automatically created under folder having same name as your Qsys system name. And these files are used during compilation in Quartus.

So if you edit your original file, it would not get reflected during Analysis and Synthesis. If you edit your original file, you need to reopen your Qsys and select 'Generate HDL' option again to let Qsys copy your updated file into 'submodules' folder.

I hope this helps.

Cheers,

Bhaumik