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junyoung2
New Contributor
New Contributorwire assignment in verilog
Hello, I have a question while I was writing the code. I made a code wire [15:0] A; and I declared input B; and I declared this signal as assign A = {8{B}};. When I declared this, the top 8 bits of signal A would be filled with 0, so why would it be filled with 0? Shouldn't it be filled with z or x??
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KennyT_alteraSuper Contributor
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- KennyT_altera
this case is close internally.
