Why does Quartus put a LE buffer cell in series with the output of an LE cell (adder cell) and the input to the downstream FF? See highlighted element in schematic. Is there a way to disable this?

I'm giving up on trying to do this on an Altera part. Two weeks of pain and frustration is all that I can tolerate. I tried every option that made sense. I even tightened the timing constraint to point of failure but still Quartus insisted on keeping the buffers. I don't know how Abe created his version without the buffers, except perhaps you are using something other than Quartus??? To me, this buffer insertion is a total waste of resources. 128 LE are being used to do this (actually many more exist in the design) and for what? Perhaps this is a bug in 18.1? Something is not right! The TDC critically depends on these buffers NOT being there, so this is a failed attempt at building a PUF on Altera FPGAs.