Why does Quartus put a LE buffer cell in series with the output of an LE cell (adder cell) and the input to the downstream FF? See highlighted element in schematic. Is there a way to disable this?

What does the code for the 12-to-1 mux look like? There must be a reason why Quartus thinks it's a clock.

As for the extra buffer delays, if turning off optimize hold timing doesn't work and you can determine (from timing analysis most likely; look at a timing report on one of those paths that have the buffer in it) why the buffers are getting added, you could try using set_max[min]_delay SDC constraints to force short routing on those paths and avoid the additional delay. It wouldn't be too bad to use since you can use wildcards to constrain all of them.

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