Why does Quartus put a LE buffer cell in series with the output of an LE cell (adder cell) and the input to the downstream FF? See highlighted element in schematic. Is there a way to disable this?

Have you tried not using a Logic Lock region? Any reason why you need it (tight timing requirement perhaps)? Buffers are inserted for some more complex design flows (like partial reconfiguration) for Logic Lock regions to reserve locations for signals going in and out of the region. That could be the case here (I don't know what part of your design is encompassed by the Logic Lock region) though I don't recall seeing this if you are not using a more complex design flow. It can't hurt to try.

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