Why does Intel Quartus Prime not permit VHDL external names in synthesizable code?

Question

VHDL external names are where we use the << and >> symbols to declare an alias to a signal in another level of hierarchy in the design. They are often used in testbench code.

It seems that this feature is not allowed in Intel Quartus Prime for synthesis. I get this error when I declare a hierarchical signal:

Error (10500): VHDL syntax error at LED.vhd(16) near text "<"; expecting an identifier, or a string literal

Why is this feature not supported for synthesis?

khaichein_y_intel · Answer

Hi,May I know the edition (Pro/Standard) and version of the software you are using?Thanks.

khaichein_y_intel · Answer

Hi,May I know if you have any updates?Thanks.

gyuunyuu · Answer

I thought I had replied already. I am using Quartus Standard 18.0.

khaichein_y_intel · Answer

Hi,

I am sorry for missing out the information. I think your reply is not reflected in the forum replies (see below)

Have you tried to compile in the Pro edition? The Standard edition has limited language support for VHDL-2008. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf.

Thanks.

gyuunyuu · Answer

I do not have license for the pro edition. It seems that this feature in the language is intended for testbenches and not intended to be supported in synthesis.

This item closes here and no more discussion is required.

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Why does Intel Quartus Prime not permit VHDL external names in synthesizable code?

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