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gyuunyuu's avatar
gyuunyuu
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7 years ago

Why does Intel Quartus Prime not permit VHDL external names in synthesizable code?

VHDL external names are where we use the << and >> symbols to declare an alias to a signal in another level of hierarchy in the design. They are often used in testbench code. It seems that this feat...
gyuunyuu's avatar
gyuunyuu
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6 years ago

I do not have license for the pro edition. It seems that this feature in the language is intended for testbenches and not intended to be supported in synthesis.

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