Forum Discussion

gyuunyuu's avatar
gyuunyuu
Icon for Contributor rankContributor
6 years ago

Why does Intel Quartus Prime not permit VHDL external names in synthesizable code?

VHDL external names are where we use the << and >> symbols to declare an alias to a signal in another level of hierarchy in the design. They are often used in testbench code. It seems that this feat...
gyuunyuu's avatar
gyuunyuu
Icon for Contributor rankContributor
6 years ago

I do not have license for the pro edition. It seems that this feature in the language is intended for testbenches and not intended to be supported in synthesis.

This item closes here and no more discussion is required.