Forum Discussion
gyuunyuu
Contributor
ContributorWhy does Intel Quartus Prime not permit VHDL external names in synthesizable code?
VHDL external names are where we use the << and >> symbols to declare an alias to a signal in another level of hierarchy in the design. They are often used in testbench code. It seems that this feat...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
I am sorry for missing out the information. I think your reply is not reflected in the forum replies (see below)
Have you tried to compile in the Pro edition? The Standard edition has limited language support for VHDL-2008. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/po/ss-quartus-comparison.pdf.
Thanks.
