Honored ContributorHello, I am currently making a design on an Altera FPGA which may become fabricated. My question is should I construct the design completely using block diagrams, and primitive gates, or should I also use Megafunctions and VHDL code to make the development faster. I have no knowledge in how to convert a FPGA design file into one that can be used for fabrication.
Honored ContributorBy fabricated, you mean you're using the FPGA to ASIC prototyping?
If so, are you going via HardCopy or via a standard cell ASIC? If you're going via HardCopy, you can just take a Stratix design and compile it to the equivalent HardCopy without changes. If you're going via a standard cell ASIC, then you'll have to use a completely different set of tools and libraries. Therefore, use only standard VHDL/Verilog as much as possible. Everything else you use will have to be replaced when you target the ASIC. You should also start getting familiar with the ASIC tools and the target process libraries too see what works on each case.Honored ContributorI will probably choose to go with the standard cell ASIC design. In that case I will need to use all VHDL code and then use some sort of software to convert it into an ASIC friendly design. Is that correct?
Honored ContributorBasically, yes.
The normal flow for a digital ASIC is to take VHDL/Verilog and to use a synthesis tool (ie, Synopsis' Design Compiler or Cadence's RTL Compiler) to synthesize it into a netlist of cells; the cell library will be provided by the foundry where you want to fabricate the ASIC.
