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Altera_Forum
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13 years ago

Which way will make fabrication easier

Hello, I am currently making a design on an Altera FPGA which may become fabricated. My question is should I construct the design completely using block diagrams, and primitive gates, or should I als...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Basically, yes.

The normal flow for a digital ASIC is to take VHDL/Verilog and to use a synthesis tool (ie, Synopsis' Design Compiler or Cadence's RTL Compiler) to synthesize it into a netlist of cells; the cell library will be provided by the foundry where you want to fabricate the ASIC.