Which way will make fabrication easier

By fabricated, you mean you're using the FPGA to ASIC prototyping?

If so, are you going via HardCopy or via a standard cell ASIC?

If you're going via HardCopy, you can just take a Stratix design and compile it to the equivalent HardCopy without changes.

If you're going via a standard cell ASIC, then you'll have to use a completely different set of tools and libraries.

Therefore, use only standard VHDL/Verilog as much as possible. Everything else you use will have to be replaced when you target the ASIC.

You should also start getting familiar with the ASIC tools and the target process libraries too see what works on each case.