WHEN with STD_LOGIC_VECTOR gives error for ''00'' but not for '0'&'0'

Well, I'm completely new VHDL and Quartus but I came across something which I don't understand while doing an assignment today. I'm writing a 2 bit multiplexer but I included only two signals here to illustrate the issue:

library ieee;
use ieee.std_logic_1164.all;
entity mux_test is
    port(
     a,b   : in std_logic;
     s     : in std_logic_vector(1 downto 0);
     x       : out std_logic );
end mux_test;
architecture behaviour of mux_test is
begin
    
    x <= a when s =''00'' else
           b;
end behaviour; 

Compiling this doesn't work, I get the error message:

Error (10500): VHDL syntax error at mux_test.vhd(16) near text "'"; expecting "(", or an identifier, or unary operator

However, if instead of when s=''00'' I write when s='0'&'0' it compiles fine and I can write a multiplexor using this notation instead. However, I don't see why the standard way of writing it doesn't work; it's used everywhere on the internet I have looked and in textbooks. Is there something I'm missing or some bug in the program? I'm using Quartus II 13.0 with Linux Mint 13 Maya.