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Altera_Forum's avatar
Altera_Forum
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12 years ago

WHEN with STD_LOGIC_VECTOR gives error for ''00'' but not for '0'&'0'

Well, I'm completely new VHDL and Quartus but I came across something which I don't understand while doing an assignment today. I'm writing a 2 bit multiplexer but I included only two signals here to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

What I see in your code is two single quotes

''
and not a double quote
"
You must use double quotes