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Altera_Forum's avatar
Altera_Forum
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12 years ago

WHEN with STD_LOGIC_VECTOR gives error for ''00'' but not for '0'&'0'

Well, I'm completely new VHDL and Quartus but I came across something which I don't understand while doing an assignment today. I'm writing a 2 bit multiplexer but I included only two signals here to...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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its because s is a null array, as you've declared it as (0 downto 1), giving a length of -1. decalre it (1 downto 0) instead and it will work with "00"

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Sorry, I think that was just a typo in my post. I still have the same problem; if I change from ''xx'' to 'x'&'x' everywhere it works.