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Altera_Forum's avatar
Altera_Forum
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11 years ago

what is the diffirent between 2 part codes

here 


process(current_state,data_in) begin
  next_state<=current_state;
  case current_state is
   when idel =>
	 if data_in='1' then
	  next_state<=d1;
	  else
	  next_state<=idel;
	 end if;
	 when d1 =>
	  if data_in='0' then
	   next_state<=d10;
		else
		next_state<=d1;
	  end if;
          .
          .
          .
       end case;
   end process;

and here 


process(current_state,data_in) begin
  next_state<=current_state;
  case current_state is
   when idel =>
	 if data_in='1' then
	  next_state<=d1;
	 end if;
	 when d1 =>
	  if data_in='0' then
	   next_state<=d10;
		end if;
	 when d10 =>
	  if data_in='1' then
	   next_state<=d101;
	  end if;
          .
          .
          .
       end case;
   end process;

it's same or diffirent ???

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    here 

    
process(current_state,data_in) begin
  next_state<=current_state;
  case current_state is
   when idel =>
     if data_in='1' then
      next_state<=d1;
      else
      next_state<=idel;
     end if;
     when d1 =>
      if data_in='0' then
       next_state<=d10;
        else
        next_state<=d1;
      end if;
          .
          .
          .
       end case;
   end process;

    and here 

    
process(current_state,data_in) begin
  next_state<=current_state;
  case current_state is
   when idel =>
     if data_in='1' then
      next_state<=d1;
     end if;
     when d1 =>
      if data_in='0' then
       next_state<=d10;
        end if;
     when d10 =>
      if data_in='1' then
       next_state<=d101;
      end if;
          .
          .
          .
       end case;
   end process;

    it's same or diffirent ???

    --- Quote End ---

    different, different states and different transitions. by the way where is the clock edge assignment?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    different, different states and different transitions. by the way where is the clock edge assignment?

    --- Quote End ---

    how, the clk edge is in another process, my code has 3 process (FSM moore), this it a part of combination logic for next_state
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    how, the clk edge is in another process, my code has 3 process (FSM moore), this it a part of combination logic for next_state

    --- Quote End ---

    as far as transition is concerned the first two transitions should be equivalent e.g.: 

    
when idel =>      
   if data_in='1' then       
         next_state<=d1;       
  --else  -- not needed       
      --next_state<=idel;      
  end if;
when d1 =>      
    if data_in='0' then        
         next_state<=d10;        
   -- else        
   -- next_state<=d1;       
   end if;

    however i have my doubts since you have a default statement at top:

    next_state <= current_state;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    as far as transition is concerned the first two transitions should be equivalent e.g.: 

    
when idel =>      
   if data_in='1' then       
         next_state<=d1;       
  --else  -- not needed       
      --next_state<=idel;      
  end if;
when d1 =>      
    if data_in='0' then        
         next_state<=d10;        
   -- else        
   -- next_state<=d1;       
   end if;

    however i have my doubts since you have a default statement at top:

    next_state <= current_state;

    --- Quote End ---

    i can understand like that: 

    
when idel =>      
   if data_in='1' then       
         next_state<=d1;            
  end if;

    in this code, if data_in is 1 then next_state will be d1, but when data_in is 0 then we dont know next_state will be 

    when idel =>      
   if data_in='1' then       
         next_state<=d1;       
         else   
         next_state<=idel;      
  end if;

    in this code, if data_in is 1 then next_state will be d1, but when data_in is 0 then next_state will be idel, so is this the different ???
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    in this code: 

    
when idel => 
   if data_in='1' then       
        next_state<=d1;            
  end if;

    if data_in = '1' transition occurs to d1

    if data is not '1' then state stays as d1 (but in your case state becomes current_state, which may still be correct or not as I don't see

    that part of your code. This is because you have default statement at top of process)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    To avoid latches and write readable code without confusion I use one process only for state machine. Others may use two. Universities prefer full list. The choice is yours...

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    as I don't see that part of your code.

    --- Quote End ---

    and what is that part ???? what i need to do ???

    PS: i think when data is not '1' then state will be current_state (idel), why it still d1 ???
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    it could be but depends...look at your simulation results and see what current_state is when data is not '1'.

    Personally I never use 3 processes or even two , never needed to anyway.

    You may get into problem of latches whenever a signal holds its value.