--- Quote Start ---
here
process(current_state,data_in) begin
next_state<=current_state;
case current_state is
when idel =>
if data_in='1' then
next_state<=d1;
else
next_state<=idel;
end if;
when d1 =>
if data_in='0' then
next_state<=d10;
else
next_state<=d1;
end if;
.
.
.
end case;
end process;
and here
process(current_state,data_in) begin
next_state<=current_state;
case current_state is
when idel =>
if data_in='1' then
next_state<=d1;
end if;
when d1 =>
if data_in='0' then
next_state<=d10;
end if;
when d10 =>
if data_in='1' then
next_state<=d101;
end if;
.
.
.
end case;
end process;
it's same or diffirent ???
--- Quote End ---
different, different states and different transitions. by the way where is the clock edge assignment?
Honored Contributor
