what is the diffirent between 2 part codes

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how, the clk edge is in another process, my code has 3 process (FSM moore), this it a part of combination logic for next_state

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as far as transition is concerned the first two transitions should be equivalent e.g.:

when idel =>      
   if data_in='1' then       
         next_state<=d1;       
  --else  -- not needed       
      --next_state<=idel;      
  end if;
when d1 =>      
    if data_in='0' then        
         next_state<=d10;        
   -- else        
   -- next_state<=d1;       
   end if;

however i have my doubts since you have a default statement at top:

next_state <= current_state;