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Altera_Forum
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11 years ago

what is the diffirent between 2 part codes

here process(current_state,data_in) begin next_state<=current_state; case current_state is when idel => if data_in='1' then next_state<=d1; else next_state<=idel; end if; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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different, different states and different transitions. by the way where is the clock edge assignment?

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how, the clk edge is in another process, my code has 3 process (FSM moore), this it a part of combination logic for next_state