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Altera_Forum
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12 years ago

What is the best approach to do pin assignments for DDR?

I have a design which use the Altera DDR3 Sdram controller IP to interface with the external DDR3 in board. The board I am using is Altera evb dsp development kit, stratix v edition (http://www.altera.com/products/devkits/altera/kit-stratix-v-dsp.html).

After I made the design, I try to do pin assignments in Pin Planner. After I setup all pin locations and I/O standard, then run the design during fitter, I got bunch of errors which seems to be similar, that I didn't use the calibrated on-chip termination. In the board dev kit, there are memory example design, when I do the pin assignments, I opened the ddr3x72 example design and compared its pin planner with mine. I can see them same. But when I open the qsf file of the example design, I can see:

set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_dq[51] -tag __ddr3_x72_qsys_mem_if_ddr3_emif_0_p0set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_dq[51] -tag __ddr3_x72_qsys_mem_if_ddr3_emif_0_p0

set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_dq[51] -tag __ddr3_x72_qsys_mem_if_ddr3_emif_0_p0

for most of pins, it set the input and output termination. I didn't see this option in pin planner. So does this means I have to write tcl into my project qsf file to configure the termination for all the pins? Is there any other better approach to do the pin assignments for the DDR3 interface?

Thanks in advance.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    For simple projects, you're only responsible for pin location assignments.

    There is an automatically generated .tcl file which applies those constraints for you. You need to run that script (once).

    http://www.altera.com/literature/hb/external-memory/emi.pdf

    Review "Table 2-1: Design Checklist" and then search for "pin_assignments.tcl" elsewhere in the document for additional instructions.

    Manually looking for and changing those assignments within the GUI is done in the "Assignment Editor", not "Pin Planner".
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    --- Quote Start ---

    For simple projects, you're only responsible for pin location assignments.

    There is an automatically generated .tcl file which applies those constraints for you. You need to run that script (once).

    http://www.altera.com/literature/hb/external-memory/emi.pdf

    Review "Table 2-1: Design Checklist" and then search for "pin_assignments.tcl" elsewhere in the document for additional instructions.

    Manually looking for and changing those assignments within the GUI is done in the "Assignment Editor", not "Pin Planner".

    --- Quote End ---

    Thanks, ted. I read the table 2-1. t mentioned:

    Add pin settings andDQgroup assignments. The wizardgenerated . tcl file includes I/O standard and pin loading constraints to your design. I made my design using Qsys. In the generated directory synthesis\submodules, I found several tcl file which are related with sdram IP, which includes :

    make_qysy_seq.tcl

    parameters.tcl

    pin_assignments.tcl

    pin_map.tcl

    report_timing.tcl

    report_timing_core.tcl

    timing.tcl

    I think "pin_assignments.tcl" is the one I need to run the Quartus ?

    Thanks.