What is the best approach to do pin assignments for DDR?

--- Quote Start ---

For simple projects, you're only responsible for pin location assignments.

There is an automatically generated .tcl file which applies those constraints for you. You need to run that script (once).

http://www.altera.com/literature/hb/external-memory/emi.pdf

Review "Table 2-1: Design Checklist" and then search for "pin_assignments.tcl" elsewhere in the document for additional instructions.

Manually looking for and changing those assignments within the GUI is done in the "Assignment Editor", not "Pin Planner".

--- Quote End ---

Thanks, ted. I read the table 2-1. t mentioned:

Add pin settings andDQgroup assignments. The wizardgenerated . tcl file includes I/O standard and pin loading constraints to your design. I made my design using Qsys. In the generated directory synthesis\submodules, I found several tcl file which are related with sdram IP, which includes :

make_qysy_seq.tcl

parameters.tcl

pin_assignments.tcl

pin_map.tcl

report_timing.tcl

report_timing_core.tcl

timing.tcl

I think "pin_assignments.tcl" is the one I need to run the Quartus ?

Thanks.