What is data[10+:4] data[10-:4]

I don't understand it.

It may help it you told where it came from.

--- Quote Start ---

I don't understand it.

It may help it you told where it came from.

--- Quote End ---

I'm find:

http://support.aldec.com/knowledgebase/article.aspx?aid=000786&show=vsa00219.htm

--- Quote Start ---

Indexed part-selects are supported. For vectors where the msb is less than the lsb (e.g. [0:15]) the following syntax is used:

little_vec [msb_base_expr +: width_expr]

This selects the width_expr number of bits starting from bit msb_base_expr. The bit range is ascending. The [2 +: 3] part-select selects bits [2:4] (i.e. three bits starting from bit 2).

For vectors where the msb is greater than the lsb (e.g. [15:0]) the following syntax is used:

big_vec [msb_base_expr -: width_expr]

This selects the width_expr number of bits starting from bit msb_base_expr. The bit range is descending. The [4 -: 3] part-select selects bits [4:2] (i.e. three bits starting from bit 4).

Expressions used in indexed part-selects must be constant expressions. This is a limitation of the current version of the simulator. LRM allows that the msb_base_exp and the lsb_base_exp vary at run time.

--- Quote End ---

You give the anwser to your question ;)

The first number is the bit to start from, then the +/- gives the direction, and the second number gives the number of bits.

Therefore [10+:4] means [10:13] and [10-:4] means [10:7]

I didn't know this kind of construction in Verilog, and I wonder if it wouldn't add confusion to a code if you start mixing it with the traditionnal vector representation...

--- Quote Start ---

I didn't know this kind of construction in Verilog, and I wonder if it wouldn't add confusion to a code if you start mixing it with the traditionnal vector representation...

--- Quote End ---

The main reason for use it is

genvar j;
generate 
        for(j=$bits(regs.io.rw);j!=0;j=j-64)begin : rw_regs
                int k=($bits(regs.io.rw)-j)/64;
                assign data = (tx_data_valid && (cpld_from.addr == {BASE_ADDR_RW,k}) )?regs.io.rw:{64{1'bz}};
        end
endgenerate

After I can add more registers to regs.io.rw without changing anything else.