Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- I don't understand it. It may help it you told where it came from. --- Quote End --- I'm find: http://support.aldec.com/knowledgebase/article.aspx?aid=000786&show=vsa00219.htm --- Quote Start --- Indexed part-selects are supported. For vectors where the msb is less than the lsb (e.g. [0:15]) the following syntax is used: little_vec [msb_base_expr +: width_expr] This selects the width_expr number of bits starting from bit msb_base_expr. The bit range is ascending. The [2 +: 3] part-select selects bits [2:4] (i.e. three bits starting from bit 2). For vectors where the msb is greater than the lsb (e.g. [15:0]) the following syntax is used: big_vec [msb_base_expr -: width_expr] This selects the width_expr number of bits starting from bit msb_base_expr. The bit range is descending. The [4 -: 3] part-select selects bits [4:2] (i.e. three bits starting from bit 4). Expressions used in indexed part-selects must be constant expressions. This is a limitation of the current version of the simulator. LRM allows that the msb_base_exp and the lsb_base_exp vary at run time. --- Quote End ---