What is data[10+:4] data[10-:4]

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I didn't know this kind of construction in Verilog, and I wonder if it wouldn't add confusion to a code if you start mixing it with the traditionnal vector representation...

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The main reason for use it is

genvar j;
generate 
        for(j=$bits(regs.io.rw);j!=0;j=j-64)begin : rw_regs
                int k=($bits(regs.io.rw)-j)/64;
                assign data = (tx_data_valid && (cpld_from.addr == {BASE_ADDR_RW,k}) )?regs.io.rw:{64{1'bz}};
        end
endgenerate

After I can add more registers to regs.io.rw without changing anything else.