Forum Discussion
Hi Vicky,
I've made successful simulation with ALTPLL core for Cyclone-4 with Native Link .
But when I'm trying to execute simulation with PLL core for Cyclone-5, then I'm getting such error:
# ** Error: (vcom-7) Failed to open design unit file "C:/Alex/my_designs/18_1/PLL/PLL_001/cyclone_V/PLL_50MHz.vho" in read mode.
# No such file or directory. (errno = ENOENT)
# End time: 13:11:25 on May 13,2019, Elapsed time: 0:00:00
# Errors: 1, Warnings: 0
# ** Error: C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vcom failed.
# Error in macro ./PLL_001_run_msim_rtl_vhdl.do line 8
# C:/intelFPGA_lite/18.1/modelsim_ase/win32aloem/vcom failed.
# while executing
# "vcom -93 -work work {C:/Alex/my_designs/18_1/PLL/PLL_001/cyclone_V/PLL_50MHz.vho}"
In addition I'm sending you another project with PLL.
What file or sequence is missing?
P.S. I've made simulation of LPM_counter with Native link for Cyclone 5 component and it works successfully...
Maybe the problem with Cyclone5 pll?