Warning: No paths found for timing analysis

I'm writing a spi module,just a receiver. Few lines,but many warnings.

The total logic elements is 0%.

Can an get a answer about how to result the problem?

Code:

module spi (input clk,

input cs,

input sdi,

output reg getdata,

output reg [7:0] recbuf

);

reg stsig = 0;

reg [3:0] reccount = 7;

always @(cs)

if(sdi) stsig = 0;

else stsig = 1;

always @(posedge clk)

begin

if(stsig && reccount<8)

begin

recbuf[reccount] = sdi;

reccount = reccount - 1;

end

else

begin

reccount = 7;

getdata = 1;

end

end

endmodule

Warnings:

Warning: Output pins are stuck at VCC or GND

Warning: Design contains 3 input pin(s) that do not drive logic

Warning: No exact pin location assignment(s) for 12 pins of 12 total pins

Warning: Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results

Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'.

Warning: No paths found for timing analysis