Warning: No paths found for timing analysis

I don't have quartus handy at the moment but I am a bit puzzled now.

I know you are creating a latch at cs but I expect warning of latches rather than zero logic.

You may try avoid the latch by inserting your cs statemet on the clock edge just like other signals.

always @ (posedge clk)

if cs...

assuming it does not affect your functionality