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Altera_Forum's avatar
Altera_Forum
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14 years ago

Warning: No paths found for timing analysis

I'm writing a spi module,just a receiver. Few lines,but many warnings. The total logic elements is 0%. Can an get a answer about how to result the problem? Code: module spi (input clk, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Yes, it does not affect my functionality.But it will increase the time the logic elements judging them.

In fact ,I am just a beginer leaning it for our Electronic Design Competition.If I can't solve the problem maybe I will get a spi communication module from our instructor.And I know FSM can work well from a book I read yesterday,but I don't want to use it while I'm leaning.

Thank you very much for your suggestion,I will try it.