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Altera_Forum's avatar
Altera_Forum
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14 years ago

Warning: No paths found for timing analysis

I'm writing a spi module,just a receiver. Few lines,but many warnings. The total logic elements is 0%. Can an get a answer about how to result the problem? Code: module spi (input clk, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

when sdi is 1, stsig becomes zero

when sdi is 0, stsig becomes one and if condition executes to assign to recbuf the zero sdi.

if sdi becomes 1 then stsid is zero and else condition executes doing nothing to recbuf.

so rebuf stays zero.