Honored ContributorEverytime I compile my design in the Quartus II software (the web edition), I get a warning that states "No clocks defined in design" even though in my .bdf file I have an altpll block with the input assigned to the pin associated with with the System Clock. What am I doing wrong?
Thanks!
Honored ContributorJust two points:
have you used shift_in input, I believe you need this to enable shift 2nd: for multiplication with 1,128 etc you can do without multipliersHonored ContributorIn the description of the function though, it says I don't have to use shift_in because I am using data[].
Also, how do you multipliy without a multiplier, this seems counter intuitive to me.Honored ContributorYou will need to set shift_in to '1' as it is enable input if you want every clk to cause a shift. This input is there for you in case you don't want to shift at some clks.
About multipliers: you better keep your design but if I want o multiply by 1 then I know the result is the input value. If I need to multiply by 2^n e.g 128 then I can shift input n bits towards MSB. You will need to accomodate the bit growth of your computation. At the moment 8 bits are multiplied and added 8 times, the bit growth is about 8 => 16(mult output) => 19(adder output) then youcan roundup to 8 bits. Though you can do some truncation earlier, entirely up to youHonored ContributorI have assumed shift_in is clk enable. Check your instantiation, and why have you chosen this optional input. You may better reinstantiate your lpm_shiftreg without any optional input so it kicks off
Honored ContributorI believe there is some fundamental mis-understanding of shift here inthis design.
I think you want to delay your input into 8 stages. So You don't need to use 8 shift registers. Rather you should use just 7 or 8 clked flipflops.Honored ContributorI didn't yet think about a correct solution for your problem. But the present usage of lpm_shiftreg is obviously the reason, why the logic is completely removed by the compiler. I suggest, that you read the respective MegaFunction manual thoroughly. In a short, lpm_shiftreg is working like this: It's either loading the parallel input to the register, if load is asserted or shifting in serial data from shiftin. Cause both inputs are unconnected, it's doing nothing.
P.S.: Only the topmost datapath, not using lpm_shiftreg, is kept.Honored ContributorThanks! I figured it out this morning that I needed to set the load to high, so it would know to the data was parallel input. Do you know if there is any logic block that is set to a constant high? Currently, all my loads are connected to a lpm_constant block which has one bit set to 1, but I think this may be giving me errors. I want to try to find a way to internally set the load to a constant high.
Honored Contributorkaz already stated, that you don't need a shift register here. You can simply connect a dff symbol to the bus, it's automatically extended to the bus width. Of course you can also use lpm_FF, if you prefer to define a MegaFunction, but it's not actually necessary.
Honored ContributorI also have the same warning:no defined clock.The code now is copied right from a textbook. Of course,there are other warnings to report,like output are stuck at GND,design contains 5 input pins that do not drive logic. How to do ,I get no idea.
Honored ContributorJust now,I found out I need to fill the Fmax box the pecific value.That warning disappeared.
