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Altera_Forum
Honored Contributor
Honored ContributorWarning: No Clocks Defined in Design
Everytime I compile my design in the Quartus II software (the web edition), I get a warning that states "No clocks defined in design" even though in my .bdf file I have an altpll block with the input...
Altera_ForumHonored Contributor
Honored ContributorYou will need to set shift_in to '1' as it is enable input if you want every clk to cause a shift. This input is there for you in case you don't want to shift at some clks.
About multipliers: you better keep your design but if I want o multiply by 1 then I know the result is the input value. If I need to multiply by 2^n e.g 128 then I can shift input n bits towards MSB. You will need to accomodate the bit growth of your computation. At the moment 8 bits are multiplied and added 8 times, the bit growth is about 8 => 16(mult output) => 19(adder output) then youcan roundup to 8 bits. Though you can do some truncation earlier, entirely up to you
