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Altera_Forum
Honored Contributor
17 years agoWarning: No Clocks Defined in Design
Everytime I compile my design in the Quartus II software (the web edition), I get a warning that states "No clocks defined in design" even though in my .bdf file I have an altpll block with the input...
Altera_Forum
Honored Contributor
17 years agoThanks! I figured it out this morning that I needed to set the load to high, so it would know to the data was parallel input. Do you know if there is any logic block that is set to a constant high? Currently, all my loads are connected to a lpm_constant block which has one bit set to 1, but I think this may be giving me errors. I want to try to find a way to internally set the load to a constant high.