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Altera_Forum
Honored Contributor
17 years agoWarning: No Clocks Defined in Design
Everytime I compile my design in the Quartus II software (the web edition), I get a warning that states "No clocks defined in design" even though in my .bdf file I have an altpll block with the input...
Altera_Forum
Honored Contributor
17 years agoI didn't yet think about a correct solution for your problem. But the present usage of lpm_shiftreg is obviously the reason, why the logic is completely removed by the compiler. I suggest, that you read the respective MegaFunction manual thoroughly. In a short, lpm_shiftreg is working like this: It's either loading the parallel input to the register, if load is asserted or shifting in serial data from shiftin. Cause both inputs are unconnected, it's doing nothing.
P.S.: Only the topmost datapath, not using lpm_shiftreg, is kept.