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Altera_Forum's avatar
Altera_Forum
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16 years ago

VHDL templates for altera

How do you ensure that a VHDL code module is optimally implemented in an Altera device?

I am aware that Quartus will do its best to ensure the compiled netlist is optimised for the current LEB architecture (eg use of clock enables, input multiplexers etc)

But are there any published templates for standard VHDL code sections that ensure this happens?

Or to put the question the other way, are there any VHDL constructs that will "confuse" Quartus and make it generate inefficient netlists?

PS I am aware of the structural options, i.e. by encapsulating lpm_xxxx modules in a VHDL wrapper. What I mean is plain behavioural or dataflow VHDL code

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Interesting topic but...

    The issue is more to do with the very heart of field design skill than the automated compiler intelligence from altera or others.

    To me, there are these few general rules:

    1) when you design remember this rule:there is a better way of doing it...find out. This is the most crucial step in planning your work.

    2) trade speed for resource.

    3) allow some freedom for compiler e.g. use case statement instead of cascaded ifs. or use select instead of cascaded else...

    4) don't wire up registers to registers. Only use registers to breakup combinatorial logic. Don't register constants, use wirs instead.

    5) instantiate or infer at the location you want. Compilers may simply follow your orders.

    6) use asynchronous reset(instead of synchronous)

    There is plenty of scattered literature but I never read it !