VHDL templates for altera

Interesting topic but...

The issue is more to do with the very heart of field design skill than the automated compiler intelligence from altera or others.

To me, there are these few general rules:

1) when you design remember this rule:there is a better way of doing it...find out. This is the most crucial step in planning your work.

2) trade speed for resource.

3) allow some freedom for compiler e.g. use case statement instead of cascaded ifs. or use select instead of cascaded else...

4) don't wire up registers to registers. Only use registers to breakup combinatorial logic. Don't register constants, use wirs instead.

5) instantiate or infer at the location you want. Compilers may simply follow your orders.

6) use asynchronous reset(instead of synchronous)

There is plenty of scattered literature but I never read it !