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Altera_Forum's avatar
Altera_Forum
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18 years ago

vhdl package not recognised

hi,

basically i am trying to do post-synthesis testing on my vhdl code, i have already written a testbench and used it with modelsim (non altera version) to do functional testing. however now i have switched to Quartus II (web edition) to perform the synthesis i have managed to setup the eda tools to launch modelsim once compilation has run and to run the testbench. (i assume gate level testing is the same as doing post-synthesis testing). the problem i am having is that the testbench uses a package which is in another vhdl file that contains functions and types, but when modelsim opens there is an error and says it cant find it in the work library. i have searched the forum for similar problems and tried them but it doesnt seem to work, i have the package in the project in Quartus II but it doesnt seem to want to compile and put it in the library with the top level entity. what solutions can you suggest?

thanks

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    In gate-level simulation, I think Nativelink doesn't compile the files in your design, so you probably need to add the package under "Test bench files". You can set the library in the Properties dialog box for each file you add.

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    thank you very much, i tried adding the package to the testbench files and it worked, however i now have a different problem, modelsim comes up with this

    # ** Warning: (vopt-1946) state_machine_vhd.sdo(145): Can't resolve SDF pathname "asynch_inst" - instance not found.

    # ** Warning: (vopt-1946) state_machine_vhd.sdo(39): Can't resolve SDF pathname "asynch_inst" - instance not found.

    # ** Warning: (vopt-1946) state_machine_vhd.sdo(57): Can't resolve SDF pathname "extena0_reg" - instance not found.

    # ** Warning: (vopt-1946) state_machine_vhd.sdo(155): Can't resolve SDF pathname "asynch_inst" - instance not found.

    # ** Warning: (vopt-1946) state_machine_vhd.sdo(72): Can't resolve SDF pathname "asynch_inst" - instance not found.

    and

    # ** Error: (vsim-SDF-3250) state_machine_vhd.sdo(35): Failed to find INSTANCE '/main_test/\clk~I\/asynch_inst'.

    # ** Error: (vsim-SDF-3250) state_machine_vhd.sdo(44): Failed to find INSTANCE '/main_test/\clk~clkctrl\'.

    # ** Error: (vsim-SDF-3250) state_machine_vhd.sdo(53): Failed to find INSTANCE '/main_test/\clk~clkctrl\/extena0_reg'.

    # ** Error: (vsim-SDF-3250) state_machine_vhd.sdo(68): Failed to find INSTANCE '/main_test/\req~I\/asynch_inst'.

    # ** Error: (vsim-SDF-3250) state_machine_vhd.sdo(77): Failed to find INSTANCE '/main_test/\req1~feeder\'.

    # ** Warning: (vsim-SDF-3432) state_machine_vhd.sdo: This file is probably applied to the wrong instance.

    # Ignoring subsequent missing instances from this file.

    # ** Warning: (vsim-SDF-3440) state_machine_vhd.sdo: Failed to find any of the 11 instances from this file.

    # ** Warning: (vsim-SDF-3442) state_machine_vhd.sdo: Try instance '/main_test/dut'. It contains all instance paths from this file.

    what could be causing these errors ?

    thank you again for the help
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Under 'Edit Test Bench Settings', did you specify "dut" in the field "Design instance name in test bench" or did you leave it blank?

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi,

    I have a very similar problem but I don't know how to find the solution. I compile,synthesize in Precision and I do the place and route in QuartusII. I want to simulate the whole project with the .vho and .sdo files in modelsim. I have written a testbench and when I tried to do the simulation I have the next errors: 

    # ** Error: (vsim-SDF-3250) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(35): Failed to find INSTANCE '/testbench/iCLK_50_ibuf/asynch_inst'.
#  ** Error: (vsim-SDF-3250) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(44): Failed to find INSTANCE '/testbench/\iCLK_50~clkctrl\'.
#  ** Error: (vsim-SDF-3250) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(53): Failed to find INSTANCE '/testbench/\iCLK_50~clkctrl\/extena0_reg'.
#  ** Error: (vsim-SDF-3250) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(68): Failed to find INSTANCE '/testbench/\iSWITCH_ibuf_0_\/inreg_D_mux'.
#  ** Error: (vsim-SDF-3250) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo(77): Failed to find INSTANCE '/testbench/\iSWITCH_ibuf_0_\/input_reg'.
#  ** Warning: (vsim-SDF-3432) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo: This file is probably applied to the wrong instance.
#  Ignoring subsequent missing instances from this file.
#  ** Warning: (vsim-SDF-3440) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo: Failed to find any of the 23 instances from this file.
#  ** Warning: (vsim-SDF-3442) C:/Documents and Settings/Jose/Escritorio/Prueba_VHDL/Prueba_temp_5/simulation/modelsim/PROBA_vhd.sdo: Try instance '/testbench/dut'. It contains all instance paths from this file.

    ¿If anybody can suggest any possible solution?

    Many thanks