VHDL: Initial values for (unconnected) input ports are ignored (Quartus Prime 20.2 Pro)

Quartus Version: Quartus Prime 20.2 Pro

Device Family: Cyclone 10 GX

Issue:

I wanted to use some of my vhdl modules, where I set initial values to input ports in the entity's port list:

...
LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY lpm;
USE lpm.all;

ENTITY counter_32updnld IS
  PORT
  (
    sload :  IN  STD_LOGIC;
    data :   IN  STD_LOGIC_VECTOR (31 DOWNTO 0);
    updown:  IN  STD_LOGIC := '1';     -- Up-counter if port is left unconnected.
    clock :  IN  STD_LOGIC;
    clk_en : IN  STD_LOGIC := '1';     -- Always enabled if port is left unconnected.
    cnt_en : IN  STD_LOGIC := '1';     -- Always enabled if port is left unconnected.
    aclr :   IN  STD_LOGIC;
    q :      OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
    cout :   OUT STD_LOGIC 
  );
END ENTITY counter_32updnld;
...

Using those vhdl modules in former Quartus Projects (lite editions) while leaving ports 'clk_en' and 'cnt_en' unconnected, the counter worked as expected.

Doing the same with Quartus Prime Pro 20.2 (and 19.4 aswell), the counter doesn't count. It seems, that unconnected ports are forced to '0' by synthesis. But I don't even get a warning or information message about that.

If I connect those ports to '1' the counter works correctly.

Is there a setting I missed?

Best regards, Harald