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HBirk's avatar
HBirk
Icon for New Contributor rankNew Contributor
6 years ago

VHDL: Initial values for (unconnected) input ports are ignored (Quartus Prime 20.2 Pro)

Quartus Version: Quartus Prime 20.2 Pro Device Family: Cyclone 10 GX Issue: I wanted to use some of my vhdl modules, where I set initial values to input ports in the entity's port list: ...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
6 years ago

Just to clarify what you're saying, you've always had those initial values set for the 3 ports, but you always left them unconnected when instantiating counter_32updnld elsewhere. Is that accurate?

Can you run a simulation or use Signal Tap to see that those inputs get set to 1 (or not) in hardware? If a signal can't be initialized, there would normally be a message or something about it. It might be hidden in the Compilation Report somewhere which would be why you didn't see it, but it's strange that this would change with 19.4. What was the last version of the software you used where it worked correctly?

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