vhdl file syntax or logic error result in that ...unable open .vcd

Hi,

I am new to Quartus II. I have created a very simple program for shift register in VHDL. It was successfully compiled. Then I create the input wave forms and saved it. When I run it, the last statement is "can not open .......filename .vcd file". the program runs fine, except at the end it states:

reading f:/altera/worklibrary/shift/shift.vwf...

reading f:/altera/worklibrary/shift/simulation/qsim/shift.msim.vcd...

unable to open f:/altera/worklibrary/shift/simulation/qsim/shift.msim.vcd

error.

the vhdl file form the textbook"eda实用教程（vhdl版）" is:

library ieee;--打开ieee库

use ieee.std_logic_1164.all;--允许ieee库中1164程序包中所有内容

entity shift is

port(

clk: in std_logic;--时钟信号

co: in std_logic;--进位输入信号

md: in std_logic_vector(2 downto 0);

d: in std_logic_vector(7 downto 0);--待加载移位的数据

qb: out std_logic_vector(7 downto 0);--led移位输出信号

cn: out std_logic);--led移位进位信号

end entity shift;

architecture bhv of shift is

signal reg:std_logic_vector(7 downto 0);

signal cy:std_logic;

begin

process(clk,co,md)

begin

if clk'event and clk='1' then

case md is

when "000" =>

reg(0)<=co;reg(7 downto 1)<=reg(6 downto 0);cy<=reg(7);--&#24102;&#36827;&#20301;&#24490;&#29615;&#21521;&#24038;&#31227;&#20301;

when "001" =>

reg(0)<=reg(7);reg(7 downto 1)<=reg(6 downto 0);--&#19981;&#24102;&#36827;&#20301;&#24490;&#29615;&#21521;&#24038;&#31227;&#20301;

when "010" =>

reg(7)<=co;reg(6 downto 0)<=reg(7 downto 1);cy<=reg(0);--&#24102;&#36827;&#20301;&#24490;&#29615;&#21521;&#21491;&#31227;&#20301;

when "011" =>

reg(7)<=reg(0);reg(6 downto 0)<=reg(7 downto 1);--&#19981;&#24102;&#36827;&#20301;&#24490;&#29615;&#21521;&#21491;&#31227;&#20301;

when "100" =>

reg(7 downto 0)<=d(7 downto 0);--&#21152;&#36733;&#24453;&#31227;&#20301;&#30340;&#25968;

when others =>

reg<=reg;cy<=cy;--&#20445;&#25345;&#19981;&#21464;

end case;

end if;

end process;

qb(7 downto 0)<=reg(7 downto 0);--led&#31227;&#20301;&#36755;&#20986;

cn<=cy;--led&#31227;&#20301;&#36827;&#20301;&#36755;&#20986;

end architecture bhv;

i think that it is probably the vhdl file syntax error or logic error.signal statements are most likely to make mistakes.

so i really need your help to solve the confused problem.

thank you very much!