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Altera_Forum's avatar
Altera_Forum
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10 years ago

vhdl file syntax or logic error result in that ...unable open .vcd

Hi, I am new to Quartus II. I have created a very simple program for shift register in VHDL. It was successfully compiled. Then I create the input wave forms and saved it. When I run it, the la...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

brr...

really? is testbench for VHDL converted to Verilog? I heard that 'reg' is reserved word for Verilog.

I don't trust anything from software guys until deep explorer.