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Altera_Forum's avatar
Altera_Forum
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10 years ago

vhdl file syntax or logic error result in that ...unable open .vcd

Hi, I am new to Quartus II. I have created a very simple program for shift register in VHDL. It was successfully compiled. Then I create the input wave forms and saved it. When I run it, the la...
Altera_Forum's avatar
Altera_Forum
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10 years ago

The problem has been solved！The real reason is key word error.

Error (146032): Syntax error encountered in vector source file F:/altera/WorkLibrary/shift/simulation/qsim/shift.msim.vcd, line 75, found text "reg"

If you replace the word 'reg' with other word like 'temp', the waveform simulation can run normally. Thanks any way, an example in the textbook has a single mistake.
Superman's avatar
Superman
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4 years ago

thank you very much!