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Altera_Forum's avatar
Altera_Forum
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10 years ago

vhdl file syntax or logic error result in that ...unable open .vcd

Hi, I am new to Quartus II. I have created a very simple program for shift register in VHDL. It was successfully compiled. Then I create the input wave forms and saved it. When I run it, the la...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Thank you! You remind me. I checked the simulation output.

quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog --write_settings_files=off shift -c shift --vector_source="F:/altera/WorkLibrary/shift/shift.vwf" --testbench_file="F:/altera/WorkLibrary/shift/simulation/qsim/shift.vwf.vt"

Fact like you said truly.