VHDL errors and question

Question

Hello! I am still learning vhdl and sorry if I made a question already answered on this forum. I am using Quartus II 8.1 web edition.  I have 2 questions:  1- I am trying to use the operators sll, srl, ror, and, (bitwise ones like in C) and I am getting compilation errors! For example, using this:  res &lt;= worda sll 2; (res type is std_logic_vector as well as worda)
Error (10327): VHDL error at Shifter.vhd(35): can't determine definition of operator ""sll"" -- found 0 possible definitions.With this:  a := a and X"0F"; (a type is integer)
Error (10327): VHDL error at Multiplier.vhd(35): can't determine definition of operator ""and"" -- found 0 possible definitions.I am using this libs:  library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;2- I would like to create a shifter, a block that can do the sll, srl, sla, sra, ror and rol. (I made some calcs to do this, because vhdl operators were giving me errors) I would like to shift it N times, so there is the word A and the N integer. I am doing it using a loop:          -- sll
        while (con /= int and con &lt; 255) loop
            aux(7 downto 1) := aux(6 downto 0);
            aux(0) := '0';
            con := con + 1;
        end loop;This is taking like 5 minutes to compile using in my project as a block (component), is there a better way to do this?  Thank you for attention!

altera_forum · Answer

You have a couple of issues:

1. You cant use sll on std_logic_vectors because the "sll" function does not exist for that type. You have to use it on unsigned/signed type from the numeric_std library.

2. In VHDL, and integer is NOT an array of bits, so you cannot do bitwise operations on them. You have to convert the integer to an unsigned/signed or std_logic_vector type.

3. You cannot use sll/rol etc if you use those libraries. Use numeric_std instead.

4. I assune you're trying to produce synthesizable code? this is NOT going to work. Loops unroll when synthesized, and because your expression is not static (ie. a constant) it will complain. Loops are essentially N bits of hardware running in parrallel.

Overall, I suggest you go and read up on digital circuit design before trying to do stuff in VHDL. It is NOT a programming language.

altera_forum · Answer

VHDL libraries are typically using for loops to realize shifters and similar functions. To be synthesizable, the number of iterations must be finite (and not too large to produce meaningful code). It's also easy to write a wrapper function, that allows a shift operation on std_logic_vectors, based on the respective numeric lib.

Generally, it's important to understand the difference between a shift by a fixed amount and a variable parameter. A fixed shift is nothing but a simple assignment of bits. You can write it as such without using libraries.

res <= worda(worda'left-2 downto 0) & "00"; -- I use worda'left, cause I don't know the actual size

A variable shift in contrast involves a multiplexer for each target bit, the effort depend on the possible range of the shift parameter.

altera_forum · Answer

Humm, thank you for the replies :p!  I am trying to make a 8-bit signed adder (then I will make it a sub/adder), but I guess its working as a unsigned one, look at my code:  library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity SubAdder is
    port(  worda: in std_logic_vector (7 downto 0);
            wordb: in std_logic_vector (7 downto 0);
            addsub: in std_logic;
            res: out std_logic_vector (7 downto 0);
            overflow: out std_logic
    );
    
end SubAdder;
architecture Func of SubAdder is
begin
process (worda,wordb,addsub)
begin
    res &lt;= worda + wordb;
end process;
end Func;But I guess its not working for negative numbers, should negative numbers be on the 2-complements form? Or the 8th bit '1' representing it as negative (+1)? I tried 81 + 01, it outputted 82 :p  Thank you again :)

altera_forum · Answer

Unsigned and signed arithmatic are identical. Signed/unsigned is just a matter of representation. The actual implementation is the same.

So x"81" + x"01" will ALWAYS output x"82" whether it it signed or unsigned. Just x"82" will represent +130 or -126

altera_forum · Answer

The main problem you have is you're using std_logic_vectors for arithmatic. They are designed to just represent a collection of bits. They have no real meaning as unsigned or signed, and could be either.  If you scrap std_logic_signed package, and instead use ieee.numeric_std instead, you get access to types unsigned and signed.  So in your case, you could write your entity:  
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity SubAdder is
    port(  worda: in signed(7 downto 0);
            wordb: in signed(7 downto 0);
            addsub: in std_logic;
            res: out signed(7 downto 0);
            overflow: out std_logic
    );
    
end SubAdder;
architecture Func of SubAdder is
begin
process (worda,wordb,addsub)
begin
  if addsub = '1' then
    res &lt;= worda + wordb;
  else
    res &lt;= worda - wordb;
  end if;
end process;
end Func;

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