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Altera_Forum's avatar
Altera_Forum
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16 years ago

VHDL errors and question

Hello! I am still learning vhdl and sorry if I made a question already answered on this forum. I am using Quartus II 8.1 web edition. I have 2 questions: 1- I am trying to use the operator...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I got it now! Anyway I will need continue to represent negative numbers in my way (80 = -1; 81 = -2; etc), because I will need to change many things :p

Thank you!

EDITED---

How do I convert unsigned to std_logic_vector?